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На 8-ой международной конференции-семинаре, совместимость и силовая электроника. Совместно с нами и другими ведущими специалистами был опубликован доклад.


New Active Clamp Circuit for Current-Fed

Galvanically Isolated DC/DC Converters

Janis Zakis1,2, Dmitri Vinnikov1, Valery Kolosov3, Evgen Vasechko3

1 Riga Technical University, Riga, Latvia

2 Tallinn University of Technology, Tallinn, Estonia

3 Scientific and Manufacturing Enterprise “Impulse”, Zaporozhye, Ukraine

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Abstract-This paper presents a new active clamp circuit (ACC) for a galvanically isolated current-fed DC/DC converter. New ACC enables reduction of power losses in transistors and diodes. In order to demonstrate the benefits of the proposed ACC the power losses of converters with traditional and new ACC were estimated and compared. In order to validate the presented theoretical assumptions a 1.5 kW laboratory setup was assembled and tested.

$1I.                    Introduction

One of the main tasks in the design and elaboration routine of power electronic equipment is to reduce power losses in circuit elements to increase the efficiency. In given paper the current-fed galvanically isolated full bridge DC/DC converter (Fig. 1) is taken for analysis, as it has advantages like higher efficiency compared to voltage-fed topologies and low input current ripple [1-3]. Nevertheless, such converters demand implementation of additional clamping circuits in order to limit the transient overvoltages on power switches [1, 4, 5] caused by energy storing in the leakage inductance of the transformer. This is a benefit for implementation of MOSFETs with lower operating voltage and drain-source resistance (Rds).

The traditional active clamp circuit (ACC) [1, 4, 5] presented in Fig. 1 includes a switch Sa, a diode Da and a capacitor Ca (topology ACC-1). In this case the stored energy in LS is absorbed by Ca through Da. After that the energy from Ca is transferred through Sa to the transformer and the load.

Fig. 1.  Current-fed galvanically isolated DC/DC converter with traditional active clamp circuit (ACC-1).


The drawback of the ACC-1 is that during the charging and discharging process of the capacitor Ca, the inductor L current through diagonal switches S1, S4 and S2, S3 changes the preferable rectangular shape to a saw teeth shape. It leads to increased power losses in switches and output diodes because of increased value of shape ratio which corresponds to the saw teeth current shape. Because of the same reason power losses increase also in elements Sa and Da.

This paper presents modification possibilities of the ACC-1 topology in Fig. 1 to provide current shape through power switches and diodes close to rectangular.

$1II.                  Operation Principle of Proposed Converter

Fig. 2 shows the current-fed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC-2). ACC-2 was derived by adding one diode Da1 and one inductor La to the ACC-1.

Fig. 2.  Current-fed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC-2).

To describe the operation principles of the proposed ACC?2 topology several assumptions were made:

$1·    input current (inductor L current) is continuous and ripple is negligible,

$1·    voltage ripple across capacitors Ca and C is negligible,

$1·    active resistance of transformer and inductor windings is zero,

$1·    magnetizing current of the transformer is equal to zero,

$1·    power switches and diodes are assumed as ideal switches.

Fig. 3 presents generalized operating waveforms of the current-fed galvanically isolated DC/DC converter with the proposed ACC-2. All the processes were analyzed in one half period (T/2), which is subdivided in three additional intervals (t1, t2, t3). Fig. 4 illustrates the states of commutating elements and direction of currents in each time interval. Also, for further analysis the inverter switches (S1…S4) will be substituted with one switch (Sd) and the diode rectifier (D1…D4) with one diode (Dm).

During the DT/2 (Fig. 4a) interval the switch Sd is being turned on and at the same time the energy is being stored in input inductor L. At this time the active clamp switch Sa is not conducting, diodes Da and Da1 are reverse biased and there is no stored energy in the inductor La.



Fig. 3.  Generalized operating waveforms of the current-fed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC-2). Dotted lines show currents of the converter with ACC-1 presented in Fig. 1.

The processes in the active clamp start with an interval t1 (Fig. 4b), when the switch Sd is opened but the diode Da becomes forward biased. The capacitor Ca is being charged with current, which is equal to the difference of the input current (IIN=IL) and the leakage inductance (LS) current IS: IC=IIN -IS. The current IS, flows through the transformer primary and raises voltage drop U*OUT=UOUT/n, where UOUT is the output voltage and n is the transformer turns ratio. Current IS grows linearly from zero up to IS=IIN in the interval t1, which can be defined as

,                             (1)

where UC is the voltage across the capacitor Ca. At the end of the interval t1 the charging current IC of the capacitor becomes equal to zero and the diode Da becomes reverse biased.

In the time interval t2 (Fig. 4c) the switch Sa is switched on and the capacitor Ca is discharged through La, LS and the primary winding of the transformer. In the time interval t2 the linearly growing current IC reaches the value

Fig. 4.  Equivalent circuits of the current-fed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC-2) accordingly to time intervals presented in Fig. 3: time interval DT/2 (a), time interval t1 (b), time interval t2 (c), and time interval t3 (d).

Stored energy in the inductor La in the interval t2 must be fully discharged up to the interval t3 (Fig. 4d). That is why the switch Sa is switched off in the interval t3. In this case energy is discharged through Da1, and the transformer to the load. The time for energy discharging from the inductance La can be expressed as

.                           (3)

Fig. 3 shows that the sum of time intervals t1, t2, t3 is equal to the time interval of conducting diagonal switches S1, S4 (or S2, S3) and can be expressed as

.                    (4)

Amplitude value of current in the interval t2 can be found from the positive and negative charge (Ampere second balance) (IIN?t1=iam?t2) of the capacitor Ca from (1), (2) as

.                       (5)

From equation systems (1)-(4) and taking into account (5) and the relation we obtain a quadratic equation which shows connection between input and output voltages (boost ratio)  and the duty cycle D:

,      (6)

From (6) we can express the boost ratio as

.    (7)

Fig. 5 presents the voltage boost ratio of converter with ACC?1 [1] and ACC-2 using (7) at following parameters: T=28 µs; n=2 and R0=82 ?.

Fig. 5.  Voltage boost ratio of the current-fed galvanically isolated DC/DC converters with different active clamp circuits:  1 – ACC-1 and ACC-2 at LS=0; 2 – ACC-1 at LS=2 µH; 3 – ACC-2 at LS=2 µH, La=10 µH.


$1III.               Experimental Results

For the verification of theoretical assumptions a 1.5 kW experimental setup was assembled in accordance with schematics shown in Fig. 2. The general operation parameters, component types and values of the experimental setup are summarized in Table I.


General Operating Parameters, Component Types and Values

Operating parameters


Input voltage, UIN

110 V

DC-link voltage, UDC

170 V

Output voltage UOUT

350 V

Switching frequency, f

30 kHz



S1 – S4, Sa


D1 – D4


Da, Da1

MUR 460




300 µH


1.3 µH


10 µH


4.7 µF


330 µF

Fig. 6b shows that the charging current (IC) of Ca (top part of the waveform) is significantly reduced in ACC-2 as compared to ACC-1 (Fig. 6a). As a result, the lower the power losses in the diode Da the lower is the discharging current of Ca (lower part of the waveform) which goes through the switch Sa (also lower losses in the switch Sa).

Fig. 6b also shows a voltage drop at the end of the pulse. In this time period (during the dead time between switching of the switch Sa and switches S1-S4) the energy is removed from the inductor La through the diode Da1 to the transformer and the load.

Fig. 7 shows that it is possible to reduce active power losses in the transformer and switches S1-S4 due to the more rectangular shape of current (at equal current average value (Fig. 7), RMS value for rectangular shape is smaller).

Also, the same transformer current shape goes through the rectifier diodes. It means that losses in diodes are also reduced.

Fig. 8 shows that ACC-2 can make the current of the power switch close to rectangular that can be later observed on the transformer waveforms.



Fig. 6.  Voltage of diode Da1 and current of capacitor Ca in case of ACC-1 (a) and ACC-2 (b).


Fig. 7.  Voltage and current of the transformer in case of ACC-1 (a) and ACC-2 (b).


Fig. 8.  Voltage and current of one inverter switch in case of ACC-1 (a) and ACC-2 (b).

$1IV.                Evaluation of Power Losses

Power losses were evaluated at the following assumptions:

$1·   current shape in the switches and diodes is not changing during regulation,

$1·   switches and diodes have equal allowable reverse blocking voltage,

$1·         power losses in wires are neglected.

Static power losses in MOSFETs can be expressed from the drain-source resistance Rds and the current Ids.RMS [6] through it

.                               (8)

The current Ids of the ACC-2 has a square shape and can be expressed as

,        (9)

In (9) the amplitude value of the switch current ISm (Fig. 3) can be expressed from the equality of average values of the square wave and the trapeze shape form in the interval        (1-D)T/2

.                        (10)

Inserting (10) in (9) and then in (8), where IIN=IOUT nM* at conditions d1/(1-D)<<1, we can obtain approximate power losses in the inverter switches The theoretical saw teeth shape waveform of Ids for the ACC-1 topology (Fig. 1) is shown in Fig. 3 with a dotted line.

The active power losses in rectifying diodes can be estimated with an average Id.av and RMS value Id.RMS value of the pulse current [6].

,                         (11)

where Ud.0 is the forward voltage drop and Rd is the differential resistance of the diode.

The pulse shape of current on each diode (D1-D4) is the same as the current (IS) pulse shape on the transformer primary (Fig. 3) and can be expressed as the average value of the output current IOUT:

.                                      (12)

From here the amplitude value of this current shape can be written as

.                           (13)

RMS value of the pulse shape current with amplitude (13) at conditions <<1 can be approximately categorized as

.                   (14)

After inserting (14), (12) in (11) we obtain power losses in the diodes of the converter with ACC-2, which are presented through one parameter (IOUT).

,           (15)

where ratio ? is the diode constant [3] .

The analysis of the quantitative data of Ud.0and Rd of the diodes according to [7] showed that ?=0.2…0.4 [7].

Power losses in ACC-2 MOSFETs can be expressed as


The duty cycle D in (15) and (16) can be obtained from (6)

.    (17)

In the same way we can obtain equations for the converter with ACC-1 with the saw teeth shape current. The active power losses in the transistors can be estimated as

,          (18)

where the duty cycle D1 can be expressed as [1]

.                          (19)

The active power losses in the rectifying diodes can be estimated as

 ,       (20)

Fig. 9 shows the theoretical loss reduction (%) of the current-fed galvanically isolated DC/DC converter with ACC-2 compared to that with ACC-1 in the range of twofold input voltage (UIN) boost (M*). The following parameters were used in the calculations: T=28 µs, n=2, R0=82 ?, ?=0.3, Ls=2 µH, La=10 µH.

Fig. 9.  Theoretical reduction of power losses (%) in the converter with ACC-2: 1- in power switches, 2- in rectifying diodes.

It should be mentioned that power losses were also reduced in the active resistance of transformer windings and in the switch Sa.

$1V.                  Comparison of Efficiency

To confirm the efficiency improvement, experiments of both approaches (Fig. 1 and Fig. 2) were carried out. Fig. 10 shows the comparison of efficiency curves of the current-fed galvanically isolated DC/DC converter with ACC-1 and ACC-2 at supply voltage range of 80…160 V, output voltage UOUT= 350 V and power P=1.5 kW. As it is seen from Fig. 10, the new proposed ACC-2 could provide the efficiency rise up to 1.5%.

Fig. 10.  Converter efficiency comparison with ACC-1 and ACC-2.

$1VI.                Conclusions

New active clamp circuit (ACC) that reduces static power losses in inverter switches and rectifier diodes of the current-fed galvanically isolated DC/DC converter was proposed. The equations for analytical evaluation of basic characteristics of the converter with proposed ACC were derived.

Theoretical estimations showed that in comparison with traditional solution the proposed ACC for the same operating conditions can effectively reduce power losses in diodes and transistors by 5-7% and 14-18%, correspondingly.

For the verification of theoretical assumptions a 1.5 kW test setup was assembled. It was experimentally validated that new proposed ACC could provide the efficiency rise up to 1.5% in comparison with traditional approach.

The proposed active clamp circuit can be successfully implemented in different kinds of current-fed converters to reduce transient overvoltages and power losses.


This research work has been supported by Latvian Council of Science (Grant 416/2012).


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