8я международная конференциясеминар совместимость и силовая электроника
На 8ой международной конференциисеминаре, совместимость и силовая электроника. Совместно с нами и другими ведущими специалистами был опубликован доклад.
New Active Clamp Circuit for CurrentFed
Galvanically Isolated DC/DC Converters
Janis Zakis^{1,2}, Dmitri Vinnikov^{1}, Valery Kolosov^{3}, Evgen Vasechko^{3}
^{1 }Riga Technical University, Riga, Latvia
^{2 }Tallinn University of Technology, Tallinn, Estonia
^{3 }Scientific and Manufacturing Enterprise “Impulse”, Zaporozhye, Ukraine
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AbstractThis paper presents a new active clamp circuit (ACC) for a galvanically isolated currentfed DC/DC converter. New ACC enables reduction of power losses in transistors and diodes. In order to demonstrate the benefits of the proposed ACC the power losses of converters with traditional and new ACC were estimated and compared. In order to validate the presented theoretical assumptions a 1.5 kW laboratory setup was assembled and tested.
$1I. Introduction
One of the main tasks in the design and elaboration routine of power electronic equipment is to reduce power losses in circuit elements to increase the efficiency. In given paper the currentfed galvanically isolated full bridge DC/DC converter (Fig. 1) is taken for analysis, as it has advantages like higher efficiency compared to voltagefed topologies and low input current ripple [13]. Nevertheless, such converters demand implementation of additional clamping circuits in order to limit the transient overvoltages on power switches [1, 4, 5] caused by energy storing in the leakage inductance of the transformer. This is a benefit for implementation of MOSFETs with lower operating voltage and drainsource resistance (R_{ds}).
The traditional active clamp circuit (ACC) [1, 4, 5] presented in Fig. 1 includes a switch S_{a}, a diode D_{a} and a capacitor C_{a }(topology ACC1). In this case the stored energy in L_{S} is absorbed by C_{a} through D_{a}. After that the energy from C_{a} is transferred through S_{a} to the transformer and the load.
Fig. 1. Currentfed galvanically isolated DC/DC converter with traditional active clamp circuit (ACC1).
The drawback of the ACC1 is that during the charging and discharging process of the capacitor C_{a}, the inductor L current through diagonal switches S_{1}, S_{4} and S_{2}, S_{3} changes the preferable rectangular shape to a saw teeth shape. It leads to increased power losses in switches and output diodes because of increased value of shape ratio which corresponds to the saw teeth current shape. Because of the same reason power losses increase also in elements S_{a} and D_{a}.
This paper presents modification possibilities of the ACC1 topology in Fig. 1 to provide current shape through power switches and diodes close to rectangular.
$1II. Operation Principle of Proposed Converter
Fig. 2 shows the currentfed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC2). ACC2 was derived by adding one diode D_{a1} and one inductor L_{a} to the ACC1.
Fig. 2. Currentfed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC2).
To describe the operation principles of the proposed ACC?2 topology several assumptions were made:
$1· input current (inductor L current) is continuous and ripple is negligible,
$1· voltage ripple across capacitors C_{a} and C is negligible,
$1· active resistance of transformer and inductor windings is zero,
$1· magnetizing current of the transformer is equal to zero,
$1· power switches and diodes are assumed as ideal switches.
Fig. 3 presents generalized operating waveforms of the currentfed galvanically isolated DC/DC converter with the proposed ACC2. All the processes were analyzed in one half period (T/2), which is subdivided in three additional intervals (t_{1}, t_{2}, t_{3}). Fig. 4 illustrates the states of commutating elements and direction of currents in each time interval. Also, for further analysis the inverter switches (S_{1}…S_{4}) will be substituted with one switch (S_{d}) and the diode rectifier (D_{1}…D_{4}) with one diode (D_{m}).
During the DT/2 (Fig. 4a) interval the switch S_{d} is being turned on and at the same time the energy is being stored in input inductor L. At this time the active clamp switch S_{a} is not conducting, diodes D_{a} and D_{a1} are reverse biased and there is no stored energy in the inductor L_{a}.
Fig. 3. Generalized operating waveforms of the currentfed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC2). Dotted lines show currents of the converter with ACC1 presented in Fig. 1.
The processes in the active clamp start with an interval t_{1} (Fig. 4b), when the switch S_{d} is opened but the diode D_{a} becomes forward biased. The capacitor C_{a} is being charged with current, which is equal to the difference of the input current (I_{IN}=I_{L}) and the leakage inductance (L_{S}) current I_{S}: I_{C}=I_{IN }I_{S}. The current I_{S}, flows through the transformer primary and raises voltage drop U^{*}_{OUT}=U_{OUT}/n, where U_{OUT} is the output voltage and n is the transformer turns ratio. Current I_{S} grows linearly from zero up to I_{S}=I_{IN} in the interval t_{1}, which can be defined as
, (1)
where U_{C} is the voltage across the capacitor C_{a}. At the end of the interval t_{1} the charging current I_{C} of the capacitor becomes equal to zero and the diode D_{a} becomes reverse biased.
In the time interval t_{2} (Fig. 4c) the switch S_{a} is switched on and the capacitor C_{a} is discharged through L_{a}, L_{S} and the primary winding of the transformer. In the time interval t_{2} the linearly growing current I_{C} reaches the value
Fig. 4. Equivalent circuits of the currentfed galvanically isolated DC/DC converter with new proposed active clamp circuit (ACC2) accordingly to time intervals presented in Fig. 3: time interval DT/2 (a), time interval t_{1 }(b), time interval t_{2 }(c), and time interval t_{3 }(d).
Stored energy in the inductor L_{a} in the interval t_{2} must be fully discharged up to the interval t_{3} (Fig. 4d). That is why the switch S_{a} is switched off in the interval t_{3}. In this case energy is discharged through D_{a1}, and the transformer to the load. The time for energy discharging from the inductance L_{a} can be expressed as
. (3)
Fig. 3 shows that the sum of time intervals t_{1}, t_{2}, t_{3} is equal to the time interval of conducting diagonal switches S_{1}, S_{4} (or S_{2}, S_{3}) and can be expressed as
. (4)
Amplitude value of current in the interval t_{2} can be found from the positive and negative charge (Ampere second balance) (I_{IN}?t_{1}=i_{am}?t_{2}) of the capacitor C_{a} from (1), (2) as
. (5)
From equation systems (1)(4) and taking into account (5) and the relation we obtain a quadratic equation which shows connection between input and output voltages (boost ratio) and the duty cycle D:
, (6)
From (6) we can express the boost ratio as
. (7)
Fig. 5 presents the voltage boost ratio of converter with ACC?1 [1] and ACC2 using (7) at following parameters: T=28 µs; n=2 and R_{0}=82 ?.
Fig. 5. Voltage boost ratio of the currentfed galvanically isolated DC/DC converters with different active clamp circuits: 1 – ACC1 and ACC2 at L_{S}=0; 2 – ACC1 at L_{S}=2 µH; 3 – ACC2 at L_{S}=2 µH, L_{a}=10 µH.
$1III. Experimental Results
For the verification of theoretical assumptions a 1.5 kW experimental setup was assembled in accordance with schematics shown in Fig. 2. The general operation parameters, component types and values of the experimental setup are summarized in Table I.
TABLE I
General Operating Parameters, Component Types and Values
Operating parameters 
Value/type 
Input voltage, U_{IN} 
110 V 
DClink voltage, U_{DC} 
170 V 
Output voltage U_{OUT} 
350 V 
Switching frequency, f 
30 kHz 
Components 

S_{1} – S_{4}, S_{a} 
IRFP260N 
D_{1} – D_{4} 
HFA15TB60 
D_{a}, D_{a1} 
MUR 460 
n 
2 
L 
300 µH 
L_{S} 
1.3 µH 
L_{a} 
10 µH 
C_{a} 
4.7 µF 
C 
330 µF 
Fig. 6b shows that the charging current (I_{C}) of C_{a} (top part of the waveform) is significantly reduced in ACC2 as compared to ACC1 (Fig. 6a). As a result, the lower the power losses in the diode D_{a} the lower is the discharging current of C_{a} (lower part of the waveform) which goes through the switch S_{a} (also lower losses in the switch S_{a}).
Fig. 6b also shows a voltage drop at the end of the pulse. In this time period (during the dead time between switching of the switch S_{a} and switches S_{1}S_{4}) the energy is removed from the inductor L_{a} through the diode D_{a1} to the transformer and the load.
Fig. 7 shows that it is possible to reduce active power losses in the transformer and switches S_{1}S_{4} due to the more rectangular shape of current (at equal current average value (Fig. 7), RMS value for rectangular shape is smaller).
Also, the same transformer current shape goes through the rectifier diodes. It means that losses in diodes are also reduced.
Fig. 8 shows that ACC2 can make the current of the power switch close to rectangular that can be later observed on the transformer waveforms.
Fig. 6. Voltage of diode D_{a1} and current of capacitor C_{a} in case of ACC1 (a) and ACC2 (b).
Fig. 7. Voltage and current of the transformer in case of ACC1 (a) and ACC2 (b).
Fig. 8. Voltage and current of one inverter switch in case of ACC1 (a) and ACC2 (b).
$1IV. Evaluation of Power Losses
Power losses were evaluated at the following assumptions:
$1· current shape in the switches and diodes is not changing during regulation,
$1· switches and diodes have equal allowable reverse blocking voltage,
$1· power losses in wires are neglected.
Static power losses in MOSFETs can be expressed from the drainsource resistance R_{ds} and the current I_{ds.RMS} [6] through it
. (8)
The current I_{ds} of the ACC2 has a square shape and can be expressed as
, (9)
In (9) the amplitude value of the switch current I_{Sm} (Fig. 3) can be expressed from the equality of average values of the square wave and the trapeze shape form in the interval (1D)T/2
. (10)
Inserting (10) in (9) and then in (8), where I_{IN}=I_{OUT }nM^{*} at conditions d_{1}/(1D)<<1, we can obtain approximate power losses in the inverter switches The theoretical saw teeth shape waveform of I_{ds} for the ACC1 topology (Fig. 1) is shown in Fig. 3 with a dotted line.
The active power losses in rectifying diodes can be estimated with an average I_{d.av} and RMS value I_{d.RMS} value of the pulse current [6].
, (11)
where U_{d.0} is the forward voltage drop and R_{d} is the differential resistance of the diode.
The pulse shape of current on each diode (D_{1}D_{4}) is the same as the current (I_{S}) pulse shape on the transformer primary (Fig. 3) and can be expressed as the average value of the output current I_{OUT}:
. (12)
From here the amplitude value of this current shape can be written as
. (13)
RMS value of the pulse shape current with amplitude (13) at conditions <<1 can be approximately categorized as
. (14)
After inserting (14), (12) in (11) we obtain power losses in the diodes of the converter with ACC2, which are presented through one parameter (I_{OUT}).
, (15)
where ratio ? is the diode constant [3] .
The analysis of the quantitative data of U_{d.0}and R_{d} of the diodes according to [7] showed that ?=0.2…0.4 [7].
Power losses in ACC2 MOSFETs can be expressed as
(16)
The duty cycle D in (15) and (16) can be obtained from (6)
. (17)
In the same way we can obtain equations for the converter with ACC1 with the saw teeth shape current. The active power losses in the transistors can be estimated as
, (18)
where the duty cycle D_{1} can be expressed as [1]
. (19)
The active power losses in the rectifying diodes can be estimated as
, (20)
Fig. 9 shows the theoretical loss reduction (%) of the currentfed galvanically isolated DC/DC converter with ACC2 compared to that with ACC1 in the range of twofold input voltage (U_{IN}) boost (M^{*}). The following parameters were used in the calculations: T=28 µs, n=2, R_{0}=82 ?, ?=0.3, L_{s}=2 µH, L_{a}=10 µH.
Fig. 9. Theoretical reduction of power losses (%) in the converter with ACC2: 1 in power switches, 2 in rectifying diodes.
It should be mentioned that power losses were also reduced in the active resistance of transformer windings and in the switch S_{a}.
$1V. Comparison of Efficiency
To confirm the efficiency improvement, experiments of both approaches (Fig. 1 and Fig. 2) were carried out. Fig. 10 shows the comparison of efficiency curves of the currentfed galvanically isolated DC/DC converter with ACC1 and ACC2 at supply voltage range of 80…160 V, output voltage U_{OUT}= 350 V and power P=1.5 kW. As it is seen from Fig. 10, the new proposed ACC2 could provide the efficiency rise up to 1.5%.
Fig. 10. Converter efficiency comparison with ACC1 and ACC2.
$1VI. Conclusions
New active clamp circuit (ACC) that reduces static power losses in inverter switches and rectifier diodes of the currentfed galvanically isolated DC/DC converter was proposed. The equations for analytical evaluation of basic characteristics of the converter with proposed ACC were derived.
Theoretical estimations showed that in comparison with traditional solution the proposed ACC for the same operating conditions can effectively reduce power losses in diodes and transistors by 57% and 1418%, correspondingly.
For the verification of theoretical assumptions a 1.5 kW test setup was assembled. It was experimentally validated that new proposed ACC could provide the efficiency rise up to 1.5% in comparison with traditional approach.
The proposed active clamp circuit can be successfully implemented in different kinds of currentfed converters to reduce transient overvoltages and power losses.
Acknowledgment
This research work has been supported by Latvian Council of Science (Grant 416/2012).
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